Fabless AI chip company

Full-custom AI chip design at 7 nm and 6 nm.

As a TSMC direct account, Chipchain is authorised for 7 nm FinFET design and has carried out 6 nm AI full-custom chip design for a top AI customer.

CHIPCHAIN Team · 13th China Cup International Regatta · Shenzhen, November 2019

Founded in Shenzhen and Taipei
2018
Our latest process. An MPW tape-out in our founding year and a full-mask tape-out the next year, both on FinFET
6 nm
FinFET process nodes in our design work: 16 nm, 12 nm, 7 nm and 6 nm
4
Direct account
TSMC

Full-custom and library characterization

Transistor-level design, where it moves the whole chip.

Full-custom applies to the critical datapath blocks; the rest of a chip uses a standard tool flow. From custom cells, library characterization and re-characterization to hand-crafted netlists, custom clock trees and manual place and route, our method has nine stages, and each closes with evidence a customer can read.

Read the methodologyLibrary characterization services

Engagement models

Hand over as much of the flow as suits your team.

Four starting points. In each, Chipchain owns every stage from the hand-off onward.

SpecificationRTLVerificationPhysical designTape-outProduction
Spec-inYou bring the requirements; we deliver production silicon.ChipchainChipchainChipchainChipchainChipchainChipchain
Netlist-inYou hand over a verified netlist; we close the design and build it.Your teamYour teamChipchainChipchainChipchainChipchain
GDS-inYou hand over signed-off layout; we tape it out and run production.Your teamYour teamYour teamYour teamChipchainChipchain
Production transferAn existing chip moves to us for production management.Your teamYour teamYour teamYour teamYour teamChipchain
  • Spec-inYou bring the requirements; we deliver production silicon.ChipchainSpecification, RTL, Verification, Physical design, Tape-out, and Production
  • Netlist-inYou hand over a verified netlist; we close the design and build it.ChipchainVerification, Physical design, Tape-out, and Production
  • GDS-inYou hand over signed-off layout; we tape it out and run production.ChipchainTape-out and Production
  • Production transferAn existing chip moves to us for production management.ChipchainProduction
Compare engagement models

Production and supply

From wafer to shelf, on one plan.

See how production works
  1. 01WaferCapacity booked with the foundry.
  2. 02Wafer probeEvery die tested before it is cut.
  3. 03AssemblyDies packaged to your footprint.
  4. 04Final testPackaged parts tested to specification.
  5. 05QualityLots checked and traceable.
  6. 06DeliveryStock held and shipped to plan.

Milestones

Built on FinFET since 2018.

Our history
  1. Incorporated in Shenzhen and Taipei

  2. Access to a 16 nm FinFET process

  3. 12 nm FinFET design kit

  4. First 16 nm tape-out, on a multi-project wafer

  5. 16 nm full-mask tape-out

  6. Authorised to use 7 nm FinFET design materials

  7. 6 nm AI full-custom chip design for a top AI customer

Trust

Built to be relied on.

Visit the trust centre
  • Quality approach

    Documented gates from specification to shipment.

  • Sourcing and handover

    Parts from their makers or authorised distributors, and every handover recorded.

  • Product security

    A published contact for reporting vulnerabilities.

Build what comes next with us.

We hire engineers who like hard problems and short feedback loops.

See careers